A pulsed-latch circuit can be modeled as a fast flip-flop. This allows conventional flip-flop designs to migrate to pulse-latch versions by simple replacement to reduce the clocking power. A step in the migration process is to insert pulsers, which generate clock pulses to drive local latches. It is desirable to minimize the number of pulsers as well as the wire length of clock routing to reduce the clocking power. Latches may be used as storage devices in memory circuits.
Memory arrays are common VLSI building blocks for many kinds of integrated circuits. One reason for the utility of memory arrays is that memory arrays can be extremely dense, resulting from their regular wiring. Memories come in many different types (RAM, ROM, EEPROM) and there are many different types of cells as well, but the basic idea and organization between them is similar. For each memory block, there are peripheral circuits, such as decoders, multiplexers, word line column select, and bit line drive circuits. Therefore, for added flexibility in operation, memory arrays such as Static Random Access Memories (SRAMs) or Dynamic Random Access Memories (DRAMs) typically would employ decoding mechanisms, for example two dimensional decoding, where a subset of the address accesses a single row of the array (the row address), and a separate subset is used to select a fraction of all the columns accessed within the row.
Memory pre-decoder circuits are employed to pre-decode portions of memory addresses prior to final decoding by a decoder. For example, a memory pre-decoder circuit may pre-decode a portion of a memory address that identifies a row of memory cells in memory. The pre-decoded portion of the memory address can be provided to a corresponding row decoder. The row decoder then selects the row in memory based on the pre-decoded portion of the memory address from the memory pre-decoder circuit.
One drawback is that a memory address input pin may be susceptible to unwanted spurious signals that may propagate through the circuit while a pulse latch based pre-decoder is active. Therefore there is a need for pulse latch based pre-decoders to be reset in order to block or keep spurious input pin changes from affecting the input memory address during a hold time requirement. This type of reset signal generation needs to give proper latching margins for pre-decoded addresses across process, voltage and temperature (PVT). Once the proper data has been latched, the latch should be deactivated. This helps ensure that the circuit is robust and can accommodate process variations. Therefore a latch reset mechanism, circuit, or signal is needed to prevent spurious data once the proper data has been latched.
These and other aspects of the invention will become apparent from the following description.